This invention relates to interfacial structures for receipt between semiconductor substrate processing chambers and substrate transfer chambers and between semiconductor substrate processing chambers and accessory attachments, and to semiconductor substrate processors.
Integrated circuitry fabrication typically involves using processing equipment having chambers which are sealed from the environment for control of the atmosphere within which substrates are processed. Some wafer processors, particularly deposition processors, utilize a substrate transfer chamber which is connected with a plurality of separate substrate processing chambers. Substrates are subjected to separate processings within individual chambers, with the substrates being moved to and from the individual processing chambers and the transfer chamber by robotic arms.
By way of example only, one existing semiconductor substrate family of processors includes the Applied Materials Centura Chemical Vapor Deposition Processors. Such processors employ a central substrate transfer chamber having a plurality of processing chambers peripherally mounted thereto. The processing chambers individually mount to the transfer chamber by metallic interface blocks or structures. Such structures include an elongated slot or passageway through which individual semiconductor substrates can be moved into and out of the respective processing chambers relative to the transfer chamber. The processings within the various chambers are typically conducted at subatmospheric pressure. The transfer chamber is typically maintained at a slightly higher subatmospheric pressure than that of the process chambers to restrict material injected into the processing chambers from entering the transfer chamber.
Further, an additional method of facilitating such is to form a gas curtain across the elongated slot/passageway within the interface block. Such is provided in the Centura processors by utilizing a single gas emission opening at one side of the passageway and which is fed by a single inert gas feeding conduit. During processing, an inert gas is emitted from the single conduit intending to flow completely across the passageway and thereby provide an effective curtain/shield to any substantial flow of processing gasses within the chamber through the passageway into the transfer chamber. Further, with the processing chamber being at a lower pressure than the transfer chamber, a substantial majority of the inert curtain gas is typically drawn into the processing chamber. Such is emitted therefrom through a vacuum line and pump associated with the respective processing chamber.
Individual processing chambers have typically, in the past, been provided at or subjected to temperatures which usually do not exceed 80xc2x0 C. The transfer chamber is typically not provided with a separate heat source intended to maintain the temperature thereof or therein at some controlled temperature. Yet, some existing and future generation processes (for example chemical vapor deposition including atomic layer deposition) are resulting in elevated processor chamber body temperatures well in excess of 80xc2x0 C. This can result in adduct and other process residue accumulations within the processing chambers. Further, and particularly with higher chamber body temperatures, cold spots may develop within the processing chamber, and particularly proximate the transfer chamber.
The invention was motivated in addressing issues such as those identified above, but is in no way so limited. The invention is only limited by the accompanying claims as literally worded without limiting or interpretative reference to the specification or drawings, and in accordance with the doctrine of equivalents.
The invention includes interfacial structures for semiconductor substrate processing chambers and substrate transfer chambers, and semiconductor substrate processors. In but one implementation, a semiconductor substrate processing chamber and substrate transfer chamber interfacial structure includes a body sized and shaped to engage with and between a semiconductor substrate processing chamber and a substrate transfer chamber. The body includes a substrate passageway extending therethrough. The passageway includes walls at least a portion of which are substantially metallic. The body includes material peripheral of the walls which is substantially non-metallic and thermally insulative. The substantially non-metallic material has mounting openings extending at least partially therein. Other aspects and implementations of an interfacial structure for semiconductor substrate processing chambers and substrate transfer chambers are contemplated.
In one implementation, a semiconductor substrate processor includes a substrate transfer chamber and a plurality of substrate processing chambers connected therewith. An interfacial structure is received between at least one of the processing chambers and the transfer chamber. The interfacial structure includes a substantially non-metallic, thermally insulative mass of material interposed between the one processing chamber and the transfer chamber. The mass is of sufficient volume to effectively reduce heat transfer from the processing chamber to the transfer chamber than would otherwise occur in the absence of said mass of material.
In one implementation, a semiconductor substrate processing chamber and accessory attachment interfacial structure includes a body sized and shaped to engage with and between a semiconductor substrate processing chamber and an accessory attachment which is exposed to the processing chamber, with the body having first and second faces. The body includes an external perimeter extending between the first and second faces. The body includes a volume in at least one cross sectional region transverse the passageway which extends to diametrically opposing portions of the perimeter. At least a majority of said cross sectional region constitutes a mass of substantially non-metallic and thermally insulative material. The mass of material is sufficient to effectively reduce heat transfer between the semiconductor processing chamber and the accessory attachment when so engaged than would otherwise occur in the absence of said mass of material when so engaged.
Other implementations and aspects are contemplated.